5-1 fact data
the MC74AC190 is a reversible bcd (8421) decade counter which features synchronous counting and asynchronous presetting. the preset feature allows the MC74AC190 to be used in programmable dividers. the count enable input, the terminal count output and the ripple clock output make possible a variety of methods of implementing multistage counters. in the counting modes, state changes are initiated by the rising edge of the clock. ? high-speed e 120 mhz typical count frequency ? synchronous counting ? asynchronous parallel load ? cascadable ? outputs source/sink 24 ma 15 16 14 13 12 11 10 2 1 3 4 5 6 7 v cc 9 8 p 0 cp rc tc pl p 2 p 3 p 1 q 1 q 0 ce u /d q 2 q 3 gnd pin names ce count enable input cp clock pulse input p 0 p 3 parallel data inputs pl asynchronous parallel load input u /d up/down count control input q 0 q 3 flip-flop outputs rc ripple clock output tc terminal count output up/down counter with preset and ripple clock n suffix case 648-08 plastic d suffix case 751b-05 plastic logic symbol pl p 0 p 1 p 2 p 3 rc tc ce cp q 0 q 1 q 2 q 3 u /d
MC74AC190 5-2 fact data functional description the MC74AC190 is a synchronous up/down bcd decade counter. it contains four edge-triggered flip-flops with internal gating and steering logic to provide individual preset, count-up and count-down operations. each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number . when the parallel load (pl ) input is low , information present on the parallel load inputs (p 0 p 3 ) is loaded into the counter and appears on the q outputs. this operation overrides the counting functions, as indicated in the mode select table. a high signal on the ce input inhibits counting. when ce is low , internal state changes are initiated synchronously by the low -to-high transition of the clock input. the direction of counting is determined by the u /d input signal, as indicated in the mode select t able. ce and u /d can be changed with the clock in either state, provided only that the recommended setup and hold times are observed. two types of outputs are provided as overflow/underflow indicators. the terminal count (tc) output is normally low . it goes high when the circuits reach zero in the count down mode or 9 in the count up mode. the tc output will then remain high until a state change occurs, whether by counting or presetting or until u /d is changed. the tc output should not be used as a clock signal because it is subject to decoding spikes. the tc signal is also used internally to enable the ripple clock (rc ) output. the rc output is normally high. when ce is low and tc is high, rc output will go low when the clock next goes low and will stay low until the clock goes high again. this feature simplifies the design of multistage counters, as indicated in figures a and b. in figure a, each rc output is used as the clock input for the next higher stage. this configuration is particularly advantageous when the clock source has a limited drive capability , since it drives only the first stage. to prevent counting in all stages it is only necessary to inhibit the first stage, since a high signal on ce inhibits the rc output pulse, as indicated in the rc t ruth t able. a disadvantage of this configuration, in some applications, is the timing skew between state changes in the first and lost stages. this represents the cumulative delay of the clock as it ripples through the preceding stages. a method of causing state changes to occur simultaneously in all stages is shown in figure b. all clock inputs are driven in parallel and the rc outputs propagate the carry/borrow signals in ripple fashion. in this configuration the low state duration of the clock must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes high. there is no such restriction on the high state duration of the clock, since the rc output of any device goes high shortly after its cp input goes high. the configuration shown in figure c avoids ripple delays and their associated restrictions. the ce input for a given stage is formed by combining the tc signals from all the preceding stages. note that in order to inhibit counting an enable signal must be included in each carry gate. the simple inhibit scheme of figures a and b doesn't apply, because the tc output of a given stage is not affected by its own ce . mode select table inputs mode pl ce u /d cp mode h l l count up h l h count down l x x x preset (asyn.) h h x x no change (hold) rc truth table inputs output pl ce tc* cp rc h l h h h x x h h x l x h l x x x h *tc is generated internally h = high voltage level l = low voltage level x = immaterial = low-to-high transition count up count down 0 1 2 3 4 5 6 7 8 15 14 13 12 11 10 9 state diagram
MC74AC190 5-3 fact data figure a: n-stage counter using ripple clock figure b: synchronous n-stage counter using ripple carry/borrow figure c: synchronous n-stage counter with parallel gated carry/borrow direction control clock enable u /d ce cp rc u /d ce cp rc u /d ce cp rc u /d ce cp rc u /d ce cp rc u /d ce cp rc direction control clock enable u /d ce cp tc u /d ce cp tc u /d ce cp tc direction control clock enable
MC74AC190 5-4 fact data clock preset clear q q j k clock preset clear q q j k clock preset clear q q j k clock preset clear q q j k logic diagram cp u /d p 0 ce p 1 p 2 p 3 pl rc tc q 0 q 1 q 2 q 3 please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. maximum ratings* symbol parameter value unit v cc dc supply voltage (referenced to gnd) 0.5 to +7.0 v v in dc input voltage (referenced to gnd) 0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) 0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage temperature 65 to +150 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions.
MC74AC190 5-5 fact data recommended operating conditions symbol parameter min typ max unit v cc supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 v cc v t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 3.0 v 150 t r , t f input rise and fall time (note 1) ac devices except schmitt inputs v cc @ 4.5 v 40 ns/v r , t f ac devices except schmitt inputs v cc @ 5.5 v 25 t r , t f input rise and fall time (note 2) act devices except schmitt inputs v cc @ 4.5 v 10 ns/v t r , t f input rise and fall time (note 2) act devices except schmitt inputs v cc @ 5.5 v 8.0 ns/v t j junction temperature (pdip) 140 c t a operating ambient temperature range 40 25 85 c i oh output current e high 24 ma i ol output current e low 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that dif fer from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v ; see individual data sheets for devices that dif fer from the typical input rise and fall times. dc characteristics symbol parameter v cc (v) 74ac 74ac unit conditions symbol parameter v cc (v) t a = +25 c t a = 40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level input voltage 3.0 1.5 2.1 2.1 v out = 0.1 v input voltage 4.5 2.25 3.15 3.15 v or v cc 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level input voltage 3.0 1.5 0.9 0.9 v out = 0.1 v input voltage 4.5 2.25 1.35 1.35 v or v cc 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level output voltage 3.0 2.99 2.9 2.9 i out = 50 m a output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 v *v in = v il or v ih 3.0 2.56 2.46 v 12 ma 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 24 ma v ol maximum low level output voltage 3.0 0.002 0.1 0.1 i out = 50 m a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 v *v in = v il or v ih 3.0 0.36 0.44 v 12 ma 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 24 ma i in maximum input leakage current 5.5 0.1 1.0 m a v i = v cc , gnd leakage current 5.5 0.1 1.0 m a v i = v cc , gnd i old 2minimum dynamic output current 5.5 75 ma v old = 1.65 v max i ohd output current 5.5 75 ma v ohd = 3.85 v min i cc maximum quiescent supply current 5.5 8.0 80 m a v in = v cc or gnd supply current 5.5 8.0 80 m a v in = v cc or gnd * all outputs loaded; thresholds on input associated with output under test. 2 maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
MC74AC190 5-6 fact data ac characteristics (for figures and waveforms e see section 3) symbol parameter v cc * (v) 74ac190 74ac190 unit fig. no. symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. min typ max min max f max maximum count 3.3 80 mhz 3-3 f max frequency 5.0 110 t plh propagation delay 3.3 2.0 1.4 2.0 15.5 ns 3-6 t plh cp to q n 5.0 1.5 9.5 2.0 11.0 t phl propagation delay 3.3 2.5 14.5 2.0 16.0 ns 3-6 t phl cp to q n 5.0 1.5 10.0 2.0 11.5 t plh propagation delay 3.3 3.5 17.0 2.0 18.5 ns 3-6 t plh cp to tc 5.0 2.5 11.5 2.0 13.0 t phl propagation delay 3.3 3.5 17.0 2.0 18.5 ns 3-6 t phl cp to tc 5.0 2.5 12.5 2.0 13.0 t plh propagation delay 3.3 2.5 11.5 2.0 13.0 ns 3-6 t plh cp to rc 5.0 2.0 7.5 2.0 9.5 t phl propagation delay 3.3 2.5 11.0 2.0 12.5 ns 3-6 t phl cp to rc 5.0 1.5 8.0 2.0 9.5 t plh propagation delay 3.3 2.5 12.0 2.0 13.0 ns 3-6 t plh ce to rc 5.0 1.5 8.0 2.0 9.0 t phl propagation delay 3.3 2.0 13.0 2.0 14.5 ns 3-6 t phl ce to rc 5.0 1.5 8.0 2.0 9.0 t plh propagation delay 3.3 2.5 14.0 2.0 15.5 ns 3-6 t plh u /d to rc 5.0 1.5 8.5 2.0 10.0 t phl propagation delay 3.3 2.5 13.0 2.0 14.5 ns 3-6 t phl u /d to rc 5.0 2.5 8.5 2.0 10.0 t plh propagation delay 3.3 3.0 12.0 2.0 13.0 ns 3-6 t plh u /d to tc 5.0 3.0 8.0 2.0 9.0 t phl propagation delay 3.3 3.0 12.0 2.0 13.0 ns 3-6 t phl u /d to tc 5.0 3.0 8.0 2.0 9.0 t plh propagation delay 3.3 2.0 15.0 1.5 17.0 ns 3-6 t plh p n to q n 5.5 2.0 10.0 1.5 11.5 t phl propagation delay 3.3 2.0 14.0 1.5 16.0 ns 3-6 t phl p n to q n 5.0 2.0 9.5 1.5 11.0 t plh propagation delay 3.3 3.0 18.0 2.0 19.5 ns 3-6 t plh pl to q n 5.0 3.0 10.5 2.0 12.5 t phl propagation delay 3.3 2.5 15.0 2.0 17.0 ns 3-6 t phl pl to q n 5.0 2.0 10.5 2.0 12.0 * voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v.
MC74AC190 5-7 fact data ac operating requirements symbol parameter v cc * (v) 74ac190 74ac190 unit fig. no. symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 0.5 0.5 ns 3-9 t s p n to pl 5.0 0 0 t h hold time, high or low 3.3 0 0 ns 3-9 t h p n to pl 5.0 0 0 t s setup time, low 3.3 6.5 7.5 ns 3-9 t s ce to cp 5.0 4.5 5.0 t h hold time, low 3.3 0 0 ns 3-9 t h ce to cp 5.0 0 0 t s setup time, high or low 3.3 8.5 9.5 ns 3-9 t s u /d to cp 5.0 5.0 6.0 t h hold time high or low 3.3 0 0 ns 3-9 t h u /d to cp 5.0 0 0 t w pl pulse width, low 3.3 5.0 5.5 ns 3-6 t w pl pulse width, low 5.0 3.5 4.0 t w cp pulse width, low 3.3 5.0 5.5 ns 3-6 t w cp pulse width, low 5.0 3.5 4.0 t rec recovery time 3.3 0.5 0.5 ns 3-9 t rec pl to cp 5.0 0 0 * voltage range 3.3 v is 3.3 v 0.3 v. v oltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter value typ unit test conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 75 pf v cc = 5.0 v
MC74AC190 5-8 fact data outline dimensions n suffix plastic dip package case 64808 issue r d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 1 8 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 1 8 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 how to reach us: usa/europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmf ax0@email.sps.mot.com touchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok road, tai po, n.t., hong kong. 85226629298 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . MC74AC190/d
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